| 摘要 |
PURPOSE: A video signal process circuit is provided to reduce necessary capacity of an output data buffer by making it possible to read data from one buffer while data is written in the buffer. CONSTITUTION: A video memory(10) stores a video signal of many fields. A data buffer for conversion stores a signal of each field read from the video memory. An IP(Interlace-to-Progressive) conversion part(40) reads the signal from the data buffer during an interval corresponding to a half of one horizontal interval of an interlaced video signal. An output data buffer stores a progressive video signal obtained by the IP conversion part during the interval corresponding thereto. A read part starts read from the output data buffer while the signal from the IP conversion part is written in the output data buffer and reads data stored in the output data buffer during the interval corresponding thereto. |
