| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an SDRAM (synchronous dynamic random access memory) controller capable of responding to a change in operation frequency such as a further increase in speed of the operation frequency (the frequency of clock signal) in the same SDRAM and SDRAM controller. <P>SOLUTION: This controller comprises a first command generation circuit 12a and a second command generation circuit 12b for generating a read command or write command at different times after generating an active command. A selector 14 selects the first command generation circuit 12a or the second command generation circuit 12b according to the frequency of the clock signal. The SDRAM 3 is controlled with the command generated by the selected command generation circuit. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
