发明名称 |
CORNER PROTECTION TO REDUCE WRAP AROUND |
摘要 |
A method and structure are provided with reduced gate wrap around to advantageously control for threshold voltage and increase stability in semiconductor devices. A spacer is provided aligned to field dielectric layers to protect the dielectric layers during subsequent etch processes. The spacer is then removed prior to subsequently forming a part of a gate oxide layer and a gate conductor layer. Advantageously, the spacer protects the corner area o the field dielectric and also allows for enhanced thickness of the gate oxide near the corners.
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申请公布号 |
US2005054174(A1) |
申请公布日期 |
2005.03.10 |
申请号 |
US20030655705 |
申请日期 |
2003.09.05 |
申请人 |
HSIAO CHIA-SHUN;KIM DONG JUN |
发明人 |
HSIAO CHIA-SHUN;KIM DONG JUN |
分类号 |
H01L21/311;H01L21/762;H01L21/8234;H01L29/423;(IPC1-7):H01L21/76 |
主分类号 |
H01L21/311 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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