| 摘要 |
A common mode voltage generating circuit has a first and a second output terminal (O1, O2) to supply a common mode voltage (Vcm) to a differential output of an amplifier stage (AMP). A first field effect transistor (T1) and a second field effect transistor (T2) have interconnected drains, and both have a source coupled to a supply terminal (Vss). A third field effect transistor (T3) has a source coupled to a drain of the first field effect transistor (T1), a drain coupled to the first output terminal (O1) and to a gate of the first field effect transistor (T1). A fourth field effect transistor (T4) has a source coupled to a drain of the second field effect transistor (T2), a drain coupled to the second output terminal (O2) and to a gate of the second field effect transistor (T2). A fifth field effect transistor (T5) has a gate for receiving a first reference voltage (Vl), and a sixth field effect transistor (T6) has a source coupled to the drain of the fifth field effect transistor (T5), a drain receiving a current (2I) from a current source (CS4), wherein the drain and the gate of the sixth field effect transistor (T6) are interconnected. The third, the fourth and the sixth field effect transistors (T3, T4, T6) have interconnected gates and are biased to operate in their saturation region. The first, second and fifth field effect transistors (T1, T2, T5) are biased to operate in their linear region. The common mode voltage generating circuit further comprises a seventh field effect transistor (T7) with a source coupled to the supply terminal (Vss), a drain coupled to the drain of the fifth field effect transistor (T5), and with a gate which receives a second reference voltage (Vh). The seventh field effect transistor (T7) is biased to operate in its linear region. Bipolar transistors may be used instead of field effect transistors.
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