发明名称 |
Parallel converter topology for reducing non-linearity errors |
摘要 |
A parallel DAC topology reduces systematic linearity errors by offsetting the digital codes inputted to the individual DACs from one another. Linearity errors that would normally add together are thus reduced.
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申请公布号 |
US2005052301(A1) |
申请公布日期 |
2005.03.10 |
申请号 |
US20030655377 |
申请日期 |
2003.09.04 |
申请人 |
MILLS REGAN N. |
发明人 |
MILLS REGAN N. |
分类号 |
H03M1/06;H03M1/66;(IPC1-7):H03M1/66 |
主分类号 |
H03M1/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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