Input reception circuit for weak high speed signal for generating several output signals, which can be processed at lower detecting speed

摘要

Circuit generated output signals are to be processed by lower detecting speed. Circuit comprises input (10) for high speed input signal (Data) and number of integration elements (C1-C4). Switch (S1) connects input to one of elements for its integration. Numerous appliances (60,62,64,66) receive each one integrated signal and transmits one of number of numerous output signals. Switch is separately controlled so that high speed input signal in each subsequent input clock interval is integrated in another integration element. - Independent claims are included for data memory and reception method.