发明名称 ERROR CORRECTION CODE GENERATION CIRCUIT AND A METHOD THEREOF, ESPECIALLY RELATED TO CALCULATING AN ERROR CORRECTION CODE AT HIGHER SPEED
摘要 PURPOSE: An ECC(Error Correction Code) generation circuit and a method thereof are provided to perform an operation based on temporarily retained intermediate data, and to update the intermediate data whenever the operation is carried out, thereby calculating an ECC at higher speed. CONSTITUTION: A PO operation circuit(171) sequentially obtains symbols of each column when DVD block data is displayed in matrix type as symbols configured in 8 bits, and operates an outer parity. A PI operation circuit(172) sequentially obtains the symbols obtained in the PO operation circuit(171), and operates an inner parity of each row. The operated results of the PI operation circuit(172) are temporarily retained in a temporary retain memory(190).
申请公布号 KR20050024618(A) 申请公布日期 2005.03.10
申请号 KR20040070188 申请日期 2004.09.03
申请人 SANYO ELECTRIC CO., LTD. 发明人 TSUKAMIZU YUICHIRO
分类号 G11B20/18;H03M13/00;H03M13/29;(IPC1-7):G11B20/18 主分类号 G11B20/18
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