| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To ensure that data arrive at an intended location at an intended time by clocking the movement of the data. <P>SOLUTION: An integrated circuit comprises a clock generator 107, synchronizing phase selection circuits 109/309 each for supplying an adjusted delay to an ASIC module 102, means for separating a phase offset into different phase adjustment step sizes in supplying the adjusted delay, means for specifying a target phase tap and a clock selection tap to transition to a target phase, and means for supplying a delayed clock pulse to a clock selection register with the use of the clock selection tap in supplying the adjusted delay to each ASIC module. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
