| 摘要 |
1,094,089. Field effect transistor circuits. INTERNATIONAL BUSINESS MACHINES CORPORATION. Oct. 5, 1966 [March 29, 1966], No. 44428/66. Heading H3T. [Also in Division G3] A current limiter circuit comprises an input terminal 16, an output terminal 20, and two field effect transistors 10, 12 interconnected as shown, the source terminal of transistor 10 being directly connected to the source terminal of transistor 12, the drain terminal of transistor 10 being connected over a resistor 18 to the gate terminal of transistor 12, and the drain terminal of transistor 12 being connected over a resistor 22 to the gate terminal of transistor 10. The Specification explains with reference to Fig. 2 (not shown), how this arrangement, which utilizes the drain-source voltage drop of one transistor to reverse bias the gate-source junction of the other transistor, effects the required current limiting, and shows that it can be operative with both A.C. and D.C. inputs. The f.e.t's. may be of the symmetrical type in which the source and drain terminals are interchangeable. |
