发明名称 CLOCK INPUT/OUTPUT DEVICE
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a clock input/output device where a duty ratio of an outputted clock is guaranteed to a value close to 50%. <P>SOLUTION: A clock input/output device is provided with three state inverters Iv1 to Iv3 and an inverter Iv4. ON resistance by a transistor of a power voltage-side (VDD) is made equal to ON resistance by a transistor of a ground voltage-side (0). Threshold voltage with which output is changed against input is set to be VDD/2. Thus, the duty ratio of the clock outputted from the clock input/output device can be guaranteed to 50%. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p>
申请公布号 JP2005064701(A) 申请公布日期 2005.03.10
申请号 JP20030290229 申请日期 2003.08.08
申请人 ROHM CO LTD 发明人 ONISHI MASAKI;FUJIWARA MASAO
分类号 G06F1/06;H03K5/04;H03K5/156;H03K19/00;H03K19/0175;H03K19/096;(IPC1-7):H03K19/017 主分类号 G06F1/06
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