| 摘要 |
PROBLEM TO BE SOLVED: To provide a test pattern generation method, a test pattern generation system, and a test pattern generation device capable of efficiently generating a test pattern which is used for testing a semiconductor integrated circuit. SOLUTION: The test pattern generation method, test pattern generation system, and test pattern generation device generate the test pattern through the use of a failure simulation execution means for executing failure simulation, and a test pattern generation means for generating the test pattern. The failure simulation execution means reads out a net list of semiconductor integrated circuits to be tested from a net list storage section and forms a failure list, performs failure setting on the basis of this failure list, executes failure simulation through the use of a predetermined test pattern, and forms an undetected failure list composed of a list of failures undetected by the failure simulation. The test pattern generation means generates the test pattern through the use of the undetected failure list. COPYRIGHT: (C)2005,JPO&NCIPI
|
