发明名称 |
PLDs providing reduced delays in cascade chain circuits |
摘要 |
The present invention provides a Programmable Logic Device (PLD) incorporating a two-input multiplexer for providing a Cascade Logic output and having a Cascade Logic input coupled to a select line. A two-input multiplexer provides the desired configurable Cascade Logic function, and an initialization circuit sets the initial value for the Cascade logic under control of an initialization configuration bit. The multiplexer that provides the Cascade Logic output also provides the desired configurable Cascade Logic function using the Look-up table (LUT) and configuration bits.
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申请公布号 |
US6864714(B2) |
申请公布日期 |
2005.03.08 |
申请号 |
US20030460040 |
申请日期 |
2003.06.10 |
申请人 |
STMICROELECTRONICS PVT. LTD. |
发明人 |
DIGARI KAILASH;DESHMUKH NITIN |
分类号 |
H03K19/173;H03K19/177;(IPC1-7):H03K19/177 |
主分类号 |
H03K19/173 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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