发明名称 Hardening logic devices
摘要 The present invention is concerned with a method and apparatus for hardening logic devices. The logic device has a plurality of memory cells forming an array connected by data lines and clock lines, and the device having a further connecting line. The method comprising: receiving data on said data lines for configuring each of the memory cells. Storing data in each of the memory cells by enabling at least one of the clock lines and when the desired data has been stored, hardening the array to fix the data by selectively connecting the data and clock lines to the further line.
申请公布号 US6864712(B2) 申请公布日期 2005.03.08
申请号 US20030426248 申请日期 2003.04.28
申请人 发明人
分类号 G11C11/412;H03K19/177;(IPC1-7):H03K19/177 主分类号 G11C11/412
代理机构 代理人
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