发明名称 Method of translating a net description of an integrated circuit die
摘要 A method of representing a net includes steps of: (a) receiving as input vertices of a net in an integrated circuit die; (b) calculating rounded coordinates having a selected resolution for each of the vertices; (c) calculating rounded coordinates having the selected resolution along the net between each of the vertices; and (d) generating as output the rounded coordinates to represent the net.
申请公布号 US6865435(B1) 申请公布日期 2005.03.08
申请号 US20030658017 申请日期 2003.09.08
申请人 LSI LOGIC CORPORATION 发明人 COWAN JOSEPH
分类号 G06F19/00;G06K9/00;(IPC1-7):G06K9/00 主分类号 G06F19/00
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