发明名称 |
Delay line with a parallel capacitance for adjusting the delay time |
摘要 |
A delay line comprising a dielectric substrate including a pair of main surfaces; a transmission line disposed on one of the main surfaces of the dielectric substrate; a ground conductor disposed on the other of the main surfaces of the dielectric substrate; and at least one of a variable capacitor and a diode being disposed on the dielectric substrate and connected in parallel to the transmission line for setting a desired delay time of the delay line. In the above delay line, the delay time can be adjusted even after the delay line is mounted on a printed circuit board, and further, the delay time can be continuously adjusted. The delay line can also be formed in a multilayer structure rather than on the above dielectric substrate.
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申请公布号 |
US6864760(B1) |
申请公布日期 |
2005.03.08 |
申请号 |
US20000583171 |
申请日期 |
2000.05.30 |
申请人 |
MURATA MANUFACTURING CO., LTD. |
发明人 |
TSURU TERUHISA;MATSUMOTO MITSUHIRO |
分类号 |
H01P9/00;(IPC1-7):H01P1/18 |
主分类号 |
H01P9/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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