MULTIPLIER, DATA PROCESSOR, AND RECORDING MEDIUM FOR LOGIC DESCRIPTION DATA

摘要

PROBLEM TO BE SOLVED: To quicken the multiplication speed by iterative multiplication by suppressing an increase of a multiplication logic scale.

SOLUTION: A multiplier generates partial products (PP0 to PP8) by a partial product generating part (2), and performs carry storage addition by a partial product adding section (3) to the partial products, and generates sum data (S) and carry data (C), and adds the sum data and the carry data by an adding circuit (4), and repeats the partial multiplication of N bit multiplicand and M/L bit partial multiplier in L cycles to acquire the multiplication result of N bit multiplicand and M bit multiplier. Then, N+M/L bit sum data being a carry storage addition result associated with the partial multiplier and multiplicand to be used in the i-th cycle and the upper N bits (undecided part) of the carry data and carry information generated by adding the sum data being the carry storage addition result in the i-th cycle and the lower M/L bits (decided part) of the carry data are added through a first feedback path 20 and a second feedback path 21 to the carry storage addition in the (i+1)th cycle.

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