发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which can adequately suppress the opposing capacitance between a dummy pattern and a wiring even when it is provided with the dummy pattern formed of the same material as the wiring material between the wirings of the same layer for flattening the area between the wiring layers. SOLUTION: As the dummy pattern 3D formed of the same material as the wiring material between the wirings (wiring patterns) 3a, 3b of the same layer, the shape thereof is reduced, in the opposing capacitance (parasitic capacitance) between at least the adjacent wirings, in comparison with the rectangularparallelopiped having the parallel surfaces to the same wiring. To be concrete, this dummy pattern 3D is formed as the rectangular pallelopiped provided with the polar surface inclined by about 45°for the adjcent wirings (wiring patterns) 3a, 3b. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005057003(A) 申请公布日期 2005.03.03
申请号 JP20030285158 申请日期 2003.08.01
申请人 SANYO ELECTRIC CO LTD 发明人 NISHIMURA HIDETAKA
分类号 H01L23/52;H01L21/3105;H01L21/3205;H01L21/768;H01L21/82;H01L23/522;H01L27/10;(IPC1-7):H01L21/320 主分类号 H01L23/52
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