发明名称 Image signal processing circuit
摘要 An interlace image signal for four fields stored in an image memory is read out on a line-by-line basis and stored in an IP conversion data buffer. An output signal is a progressive image signal whose one horizontal period is twice that of an interlace image signal which is an input signal. Accordingly, reading of data from the IP conversion data buffer is made to correspond to one horizontal period on the output side at the time of outputting, and the signal which is read out is subjected to IP conversion and written into an output data buffer. By reading data from the output data buffer while data is being written into the output data buffer, the capacity of the output data buffer can be reduced to that corresponding to two horizontal lines.
申请公布号 US2005046743(A1) 申请公布日期 2005.03.03
申请号 US20040933001 申请日期 2004.09.02
申请人 SAITO SATORU 发明人 SAITO SATORU
分类号 H04N7/01;H04N5/44;(IPC1-7):H04N11/20 主分类号 H04N7/01
代理机构 代理人
主权项
地址