发明名称 Bond pad techniques for integrated circuits
摘要 The present invention provides methods for fabricating bond pads that can be employed for fabricating solder bumps and wire bonds, as well as structures containing the bond pads. Bond pads of the present invention include a contiguous interconnect line, fabricated in a dielectric layer such that the bond pad and line are exposed. A passivation layer is then deposited on the dielectric layer, the bond pad and the interconnect line. A passivation hole is etched in the passivation layer such that the hole exposes at least a portion of the bond pad. The bond pad and contiguous interconnect line can be provided with a metal overcoat layer on the top surface of the bond pad, and a barrier/seed layer on the bottom and side surfaces of the bond pad and the contiguous interconnect line.
申请公布号 US2005048772(A1) 申请公布日期 2005.03.03
申请号 US20030654240 申请日期 2003.09.02
申请人 APPLIED MATERIALS, INC. 发明人 PAN JUDON TONY
分类号 H01L21/44;H01L21/60;H01L23/485;H01L23/532;(IPC1-7):H01L21/44 主分类号 H01L21/44
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