发明名称 Defect analysis sampling control
摘要 A defect analysis sampling control system comprising a base setting module, a lot setting module, and a work in process (WIP) prediction module. The base setting module is used for choosing and setting a corresponding sampling rule in accordance with different semiconductor products and the lot setting module is used for choosing and setting a corresponding lot sampling rule in accordance with a product lot. The work in process (WIP) prediction module records all WIP products to provide status and progress of the WIP product. The present invention can be applied to a variety of products so as to control and adjust the sampling rule for all products more conveniently and arrange the sampling rules more flexibly.
申请公布号 US2005049737(A1) 申请公布日期 2005.03.03
申请号 US20040918413 申请日期 2004.08.16
申请人 LIN CHIN-HSIANG;SHIH CHING-CHENG 发明人 LIN CHIN-HSIANG;SHIH CHING-CHENG
分类号 G01N21/88;G01N37/00;G05B19/418;G06F19/00;H01L21/66;(IPC1-7):G06F19/00 主分类号 G01N21/88
代理机构 代理人
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