| 摘要 |
PROBLEM TO BE SOLVED: To provide a signal detecting circuit for suppressing power consumption while enhancing an effectual operation speed or a sampling resolution. SOLUTION: Input signal Vin are supplied to a plurality of clock type signal comparing sections 5. Clock signals CLK1, CLK2 and CLK3 having different phases have been inputted in the comparing circuits 5. These clock signals are generated in a multi-phase signal generating circuit 6. The signals detected by comparing circuits 5 are synthesized by a signal synthesizing circuit 7 and formed into detecting signals. By providing the plurality of comparing circuits 5, the sampling frequency of each of the comparing circuits 5 can be lowered. In this way, the problem can be solved that, when signals having narrow widths are captured without being missed in detecting the arrival of signals, the sampling frequency becomes high and power consumption becomes extremely large. COPYRIGHT: (C)2005,JPO&NCIPI
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