| 摘要 |
In a semiconductor circuit apparatus and its test method according to embodiments of the present invention, the clock enable control circuit can generate in a test mode an enable clock signal by using the substitute enable signal instead of the enable signal output from the enable signal generation combinational circuit and supplies it to the enable input terminal of the sequential circuit. Accordingly, with the simple structure in which the substitute enable signal is used, a proper enable clock signal can be generated and a scan test can be performed by reliably setting the sequential circuit to the enable state.
|
