Fabrication of self-aligned 1 bit silicon oxide nitride oxide silicon memory cell, by etching portions of upper oxide layer and nitride layer of oxygen-nitride-oxide layer on insulating layer pattern, using self-aligned etching spacers

摘要

A self-aligned 1 bit silicon oxide nitride oxide silicon cell is fabricated by etching portions of an upper oxide layer and nitride layer (208) of oxygen-nitride-oxide layer on an insulating layer pattern (220), using self-aligned etching spacers as an etch mask. Fabrication of a self-aligned 1 bit silicon oxide nitride oxide silicon (SONOS) cell comprises: forming an insulating layer pattern having a rectangular shape with two opposing sidewalls, on a semiconductor substrate (200); forming an oxygen-nitride-oxide (ONO) layer including a lower oxide layer (207), a nitride layer, and an upper oxide layer on the semiconductor substrate and the insulating layer pattern, the ONO layer having a uniform thickness; forming self-aligned etching spacers on both sidewalls of the insulating layer pattern; etching portions of the upper oxide layer and nitride layer of ONO layer on the insulating layer pattern, using the self-aligned etching spacers as an etch mask; removing the self-aligned etching spacers; removing the upper oxide layer exposed by the removing of the self-aligned etching spacers, and lower oxide layer of ONO layer on the semiconductor substrate; forming an oxide layer on a resultant structure on the semiconductor substrate; and forming a word line (212) for a gate of SONOS cell, using the sidewalls of the insulating layer pattern as a sidewall for the word line. An independent claim is also included for a self-aligned 1 bit SONOS cell, comprising a doped drain region (205) for a drain formed in a predetermined portion of a semiconductor substrate; an insulating layer pattern that forms a sidewall of a word line, and being on the doped drain region; a doped source region (213) on a predetermined portion of the semiconductor substrate, and separated from the doped drain region by an interposing channel region; an ONO layer disposed on one sidewall of the insulating layer pattern and on a portion of the channel region; a gate insulating layer (211) formed on the channel region where the ONO layer is not formed; and a spacer-shaped word line for a gate disposed on the ONO layer disposed on the sidewall of the insulating layer pattern, and on upper surfaces of the ONO layer and gate insulating layer.