| 摘要 |
PROBLEM TO BE SOLVED: To provide a shallow trench isolation/formation method of embodying both a transistor and a separation region in a weak topology and forming a gate line that includes an input gate terminal on an upper layer. SOLUTION: Only a pad oxide is eliminated using a STI pattern, and an isolation region is formed by implanting ion after forming a VTN pattern and a VTP pattern, thus suppressing the generation of a poly residue caused by a difference in level between a field region and a moat region as well as preventing the generation of leakage current. When voids are formed in the field region, leakage current is prevented that is caused by a poly penetrating therein. When the difference in level between the field region and moat region is reversed, a moat pit is prevented that occurs in the moat region which is opened in advance of poly etching, thus preventing a damage to the field region caused by misalignment during contact etching which is performed after a nitride side wall is formed on an upper portion of the isolation region. COPYRIGHT: (C)2005,JPO&NCIPI
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