| 摘要 |
A semiconductor memory device includes word lines, bit line pairs, memory cells 1, bit line precharge circuits 2, and write amplifiers 3, as well as a dummy word line, a dummy bit line pair, dummy memory cells 1a, 1b, and 1c, and a memory cell storing node detection circuit 6. Through the action of the dummy memory cells 1b and 1c, it is ensured that the write timing for the dummy memory cell 1a is substantially identical to the write timing for the memory cells 1. Based on changes in the states of storing nodes S1 and S2 included in the dummy memory cell 1a, the memory cell storing node detection circuit 6 generates a write completion signal WRST. As a result, a semiconductor memory device having an optimized write timing and low power consumption is provided.
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