发明名称 Selective polysilicon stud growth
摘要 A memory cell includes a bit line contact feature that is characterized by a contact hole bounded by insulating side walls including first and second pairs of opposing insulating side walls. The first pair of opposing insulating side walls comprises respective layers of insulating spacer material formed over a conductive line. The second pair of opposing insulating side walls comprises respective layers of insulating material formed between respective contact holes. The contact hole is filled to an uppermost extent of the insulating side walls with a conductively doped polysilicon plug defining a substantially convex upper plug surface profile. The contact hole may define either a bitline contact or a storage node contact.
申请公布号 US6861691(B2) 申请公布日期 2005.03.01
申请号 US20030649507 申请日期 2003.08.26
申请人 MICRON TECHNOLOGY, INC. 发明人 TRAN LUAN
分类号 H01L21/8242;H01L27/02;(IPC1-7):H01L27/108;H01L27/76 主分类号 H01L21/8242
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