发明名称 Buffer metal layer
摘要 An integrated circuit having a top passivation layer and bonding pads, where the improvement is a metal layer overlying all of the integrated circuit. The metal layer overlies the top passivation layer and is not in electrical contact with any of the bonding pads. In this manner, there is a structure that is added to the integrated circuit which has a relatively high thermal conductivity, and which also has a relatively high structural strength. With these two added properties, the occurrence of stress cracks, such as those induced by plastic molded packages, is reduced, and hot spots tend to be dissipated. Thus, the overlying metal layer tends to improve the reliability of the integrated circuit.
申请公布号 US6861343(B2) 申请公布日期 2005.03.01
申请号 US20020267410 申请日期 2002.10.09
申请人 CHIA CHOK J.;LOW QWAI H.;RANGANATHAN RAMASWAMY 发明人 CHIA CHOK J.;LOW QWAI H.;RANGANATHAN RAMASWAMY
分类号 H01L23/367;H01L23/373;H01L23/522;(IPC1-7):H01L21/44 主分类号 H01L23/367
代理机构 代理人
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