| 摘要 |
A gate wire is formed on the insulating substrate. The gate wire has gate lines, first and second gate electrodes connected to the gate lines, and gate pads. A gate insulating layer, first and second semiconductor layers and an ohmic contact layer are sequentially formed thereon. A data wire is formed on the ohmic contact layer. The data wire has first and second data lines, data line connectors, first and second source electrodes, first and second drain electrodes, and data pads. A passivation layer is formed on the data wire, and has contact holes respectively exposing the first and the second drain electrodes, and the gate and the data pads. Pixel electrodes, and subsidiary gate and data pads are formed on the passivation layer. As described above, the data line is provided at opposite sides of the pixel area so that variation in the pixel voltage due to the parasitic capacitance between the partitioned areas with different degree of misalignment is reduced. In addition, two TFTs are provided in each pixel area so that the parasitic capacitance between the gate and the drain electrodes in two respective partitioned areas with left-biased and right-biased misalignment is kept to be constant. In this way, the pixel voltage variation between the two partitioned areas is reduced to prevent non-uniformity in the brightness. |
