| 摘要 |
1,204,509. Selective signalling; counters. INFOTRONICS CORP. 30 Sept., 1967, No. 44634/67. Headings G4A and G4H. [Also in Division H3] A signal peak integrator, e.g. of the type used in chromatography analysis includes a voltage to frequency converter 20 feeding a counter 55, a variable gain amplifier 15 for range-changing, and a variety of noise rejection and correction circuits, of which the base line correction circuit 50 is only rendered active between signal peaks. Range switching.-A pair of triggers in level sensor 25 are set to respond to different voltages, e.g. 25 V and 2 V after amplification. The gain of amplifier 15 is reduced by a factor of 10 when the first trigger responds, thereby reducing the amplified signal to 2À5 V, and the high gain condition is not restored until the amplified signal drops to 2 V, so that hunting is avoided. In the low gain condition switch 56 feeds pulses to the units decade of counter 55, but in the high gain condition, pulses are fed directly to the tens decade. A delay is introduced when decade switching to avoid errors caused by the finite response time of amplifier 15. Peak detection.-RC network 24 differentiates the input signal and amplifier 28 provides a signal above or below a reference level to set one of triggers 34, 35 depending on the direction of slope of the input. The slop detection circuit is disabled by level sensor 25 during the central, high value portion of each peak. Amplifiers 21, 28 include noise rejection filters. Base line drift correction.-During the intervals between peaks the output of converter 20 drives a servo system 46, 47 to adjust a potentiometer 48 if this is necessary to bring the output frequency of converter 20 to a predetermined value. Noise rejection &c.-Plateau timer 80 detects a positive slope followed by an indeterminately long zero slope to stop the counting and reset the counter and memory 60. Minimum peak timer similarly prevents the integration of short noise spikes. Threshold level detector 84, in conjunction with peak detector 41 detect the occurrence of a large peak overlapping a smaller following peak, i.e. when, at the end of a peak, the output of converter 20 is greater than its base line value, and restarts the counter 55 read-out and counting cycle so that both peaks are integrated separately. Positive re-entry circuit 86 performs a similar function for small unresolved peaks preceding large peaks. Counter.-In the high gain condition pulses on lead 45 are fed via NOR gate 400, Fig. 4B to the units decade. On reaching a count of 9, the units decade opens NOR gate 403 to inhibit NOR gate 402 and enable NOR gate 401 so that the next pulse on lead 45 advances the units and tens decades by one via gates 400, 401. In the low gain condition, lead 95 receives a binary one to inhibit NOR 402 and enable NOR 401 so that input pulses, each representing 10 units are supplied directly to the tens dacade. The units decade also continues to count, but the carry circuit is disabled. (For Figures see next page.) |
