SEMICONDUCTOR DEVICE FOR IMPROVING LATCH-UP STRENGTH AND REDUCING PATTERN AREA

摘要

PURPOSE: A semiconductor device is provided to improve the latch-up strength and reducing a pattern area by separating a deep N-type well therefrom to prevent a conducting state of a parasitic thyristor. CONSTITUTION: A semiconductor substrate(20) is formed with a first conductivity type. A second conductive type first well(13) and a second conductive type second well(14) are formed on a surface of the semiconductor substrate, respectively. The second conductive type second well is separated from the second conductive type first well. A first conductive type third well(11) is formed in the second conductive type first well. A second conductive type fourth well(12) is formed in the second conductive type second well. A second conductive channel type MOS transistor(Mn) is formed on a surface of the first conductive type third well. A first conductive type MOS transistor(Mp) is formed on a surface of the second conductive type fourth well.