| 摘要 |
PURPOSE: A spread spectrum clock generator is provided to prevent reduction of a setup/hold time margin between data and a clock by changing simultaneously a frequency of the clock and a data delay. CONSTITUTION: A shift register(40) is used for counting an input signals and has a circular shifting function for shifting the input signals when the input signals approach high states. A delay unit is formed with a plurality of NAND gates and a plurality of inverters and is used for outputting spread signal clocks by delaying the input signals corresponding to data of bit streams of the shift register. The delay unit includes first to fifth NAND gates(41a-41e) connected to each bit stream of the shift register, a sixth NAND gate(41f) for receiving an output signal and a reference signal of the first NAND gate(41f), a first inverter(4g) for inverting an output signal of the sixth NAND gate, a seventh NAND gate(41h) for receiving an output signal of the first inverter and an output signal of the second NAND gate, a second inverter(41h) for inverting an output signal of the seventh NAND gate, an eighth NAND gate(41j) for receiving an output signal of the second inverter and an output signal of the third NAND gate. a third inverter(41i) for inverting an output signal of the eighth NAND gate, a ninth NAND gate(41l) for receiving an output signal of the third inverter and an output signal of the fourth NAND gate, a fourth inverter(41k) for inverting an output signal of the ninth NAND gate, a tenth NAND gate(41n) for receiving an output signal of the fourth inverter and an output signal of the fifth NAND gate, and a fifth inverter(41m) for inverting an output signal of the tenth NAND gate.
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