| 摘要 |
FIELD: power engineering. ^ SUBSTANCE: proposed cascaded voltage amplifier has two bridge circuits each incorporating two diodes and two capacitors. Outputs of bridge circuits are connected in phase opposition. Each output lead of either bridge circuit is connected to output diode. Interconnected leads of output diodes form first-stage output. Each output lead of bridge circuit is connected to one output lead of respective identical additional bridge circuit whose second output lead is connected to lead of additional output diode. Additional output diodes have their other leads connected to respective additional output diodes of other additional bridge circuit and to ripple capacitor to organize output of next stage. Input of each additional bridge circuit formed by interconnection of two diodes is connected through capacitor to respective input of bridge circuit. Output lead of next additional bridge circuit identical to first one and connected in same way as first additional bridge circuit to organize output of next stage is connected to output lead of each additional bridge circuit connected to additional output diode. As an alternative, each respective additional bridge circuit is connected across two diagonally opposite junctions of first output lead of first bridge circuit and second output lead of second bridge circuit, as well as second output lead of first bridge circuit and first output lead of second bridge circuit. Each additional bridge circuit has two diodes inserted in opposite arms of additional bridge circuit and capacitors are inserted in two other opposing arms, like-polarity diodes of bridge circuit and additional bridge circuit being connected cumulatively. Each output lead of second pair of diagonally opposite junctions of bridge circuit is connected to additional output diode, additional output diodes being interconnected in pairs through other leads. Interconnected leads of additional output diodes form output leads of next stage which are connected to ripple capacitor. Output of next stage is organized like that of first alternative. ^ EFFECT: enhanced multiplier efficiency for organizing several different voltage levels at output. ^ 4 cl, 5 dwg |
