Sampling rate converter for e.g. frequency-lock loop application, has chain of cells, where each cell has multipliers that have inputs connected to respective cell inputs via respective paths having preset number of flip flops

摘要

The converter has a chain of cells, where each cell has a set of inputs (IN1(n), IN1(n), IN2(n), IN3(n)) and a set of outputs for digital values. Each cell has a pair of multipliers (n3, n7) that has inputs connected to the respective inputs of the cell. The multiplier inputs are connected to the cell inputs via respective paths having a preset number of flip flops (n2, n6). - An INDEPENDENT CLAIM is also included for a method of sampling digital values using a sampling rate converter.