发明名称 Cache and memory architecture for fast program space access
摘要 A data handling system includes a memory that includes a cache memory and a main memory. The memory further includes a controller for simultaneously initiating two data access operations to the cache memory and to the main memory by providing a main memory access address with a time-delay increment added to a cache memory access address based on an access time delay between an initial data access time to the main memory relative to the cache memory. The main memory further includes a plurality of data access paths divided into a plurality of propagation stages interconnected between a plurality of memory arrays in the main memory wherein each of the propagation stages further implementing a local clock for asynchronously propagating a plurality of data access signals to access data stored in a plurality memory cells in each of the main memory arrays. The data handling system further requests a plurality sets of data from the memory wherein the cache memory is provided with a capacity for storing only a first few data for the plurality sets of data with remainder of data of the plurality sets of data stored in the main memory and the main memory and the cache memory having substantially a same cycle time for completing a data access operation.
申请公布号 US2005038961(A1) 申请公布日期 2005.02.17
申请号 US20040916089 申请日期 2004.08.10
申请人 CHEN CHAO-WU 发明人 CHEN CHAO-WU
分类号 G06F12/08;(IPC1-7):G06F12/00 主分类号 G06F12/08
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