| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a PLL circuit which can shorten a response time during starting without sacrificing the stable operation of the PLL circuit. <P>SOLUTION: The PLL circuit is provided with a voltage controlled oscillator in which a frequency of an output clock is controlled by a voltage, a frequency divider which performs the frequency dividing of an output signal of the voltage controlled oscillator, a phase comparator which compares the phase of a feedback signal outputted from the frequency divider and the phase of a reference signal, a charge pump circuit driven by an output signal of the phase comparator, and a loop filter which gives an output obtained by the integration of an output of the charge pump circuit to the voltage controlled oscillator. In the PLL circuit, a means is arranged which changes an output current of the charge pump circuit corresponding to the ratio of frequencies of the reference signal and the feedback signal during starting or at the time of a frequency setting change, so that a response time is shortened. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
