| 摘要 |
PROBLEM TO BE SOLVED: To reduce the area of a FIFO type memory. SOLUTION: A flag generating circuit has an address coincidence detecting circuit 151 for detecting coincidence of a write-in address and a read-out address, a first latch circuit 152 for forming an empty flag on the basis of an output signal of the address coincidence detecting circuit , and a second latch circuit 152 for forming a full flag based on an output signal of the address coincidence detecting circuit. Further, the circuit has control logic 154, 155 by which it is prevented that the output signal of the address coincidence detecting circuit is transmitted to the second latch circuit based on formation of the empty flag and it is prevented that the output signal of address coincidence detecting circuit is transmitted to the first latch circuit on the basis of the formation of the full flag. A counter for counting capacity of the FIFO type memory is not required. COPYRIGHT: (C)2005,JPO&NCIPI
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