| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To perform a timer process and a reception process through the low-speed action of a CPU by imparting low-speed clocks in a standby mode. <P>SOLUTION: When the standby mode is set by a mode signal MD coming from the CPU 50, FFs 12, 25 are reset to stop a high-speed clock source 13 while low-speed clocks LCK are selected by a selection signal SL and supplied to the CPU 50 as clock signals CLK. The CPU 50 thereby shifts to the standby mode. At the input of an interrupt signal INT, FFs 12, 19 are set to start the high-speed clock source 13 and a counter 21 starts counting low-speed clocks LCK. Once the count value CNT of the counter 21 has reached a set value of a register 23, the FF 25 is set and high-speed clocks HCK are selected by the selection signal SL. Thereby stable high-speed clocks HCK are supplied to the CPU 50 to start an interrupt process. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
