| 摘要 |
PROBLEM TO BE SOLVED: To shorten the processing time required for the processing of verifying a circuit to be tested on the basis of test patterns of a number larger than that of the memory maximum length of a memory for storing the test patterns without increasing load on a test apparatus. SOLUTION: In a test pattern load device 30, the test patterns to be executed are divided into a size storable in the memory 11 for storing the test patterns and stored in parallel and horizontal directions in the memory 11 for storing the test patterns, and test program information indicating the location of storage and division information on the number of divisions etc. are reported to a verification processing part 13. In the verification processing part 13, the number of division of the test patterns and the location of its storage stored in the memory 11 for storing the test patterns are recognized on the basis of the division information, and read regions from the memory 11 for storing the test patterns are sequentially changed by a read region switch circuit 12 to read each test vector and verify the circuit to be tested 20 accordingly. COPYRIGHT: (C)2005,JPO&NCIPI
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