发明名称 VITERBI DECODER
摘要 PROBLEM TO BE SOLVED: To provide a Viterbi decoder which is capable of dealing with a plurality of kinds of restrict lengths and the number of coefficients for an arbitrary estimate transmission line and can be composed of dedicated hardware of a small circuit scale. SOLUTION: Branch metrics of all paths from the state at a previous time to the state at the present time are operated, a most tolerant path is selected out of the paths to the respective states by a branch metric 101a and a path metric 103a, and a path select signal 102a and a path metric 102b are outputted. A path metric storage device 103 outputs the path metric 103a to be inputted to an ACS arithmetic unit 102 when performing the ACS arithmetic at the next time. A temporary path select signal storage device 104 stores the path select signals 102 as many as (n) states, outputs the path select signals 104a as many as (m) states ((m)≤(n)), and changes the input bit position in accordance with the encoding restrict length for a system to which Viterbi decoding is applied, or the estimated number of coefficients for the estimate transmission line. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005045727(A) 申请公布日期 2005.02.17
申请号 JP20030280274 申请日期 2003.07.25
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 TAKAGI NOBUHIRO
分类号 G06F11/10;H03M13/41;H04L1/00;(IPC1-7):H03M13/41 主分类号 G06F11/10
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