| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a clock reproducer circuit which causes neither jitter nor pulse loss, even if the duty ratio of input data deviates over 50% of an ideal value. <P>SOLUTION: The reproducer circuit switches over the high and low of a positive and negative logical outputs of a toggle flip flop with either the rise or fall of input data as a trigger, inputs the positive and negative logic outputs of the toggle flip flop to the gates of a first and second gated oscillator circuits as gating signals for oscillation/stop, and operates a combiner circuit to arithmetically process the logical sum on the outputs of the first and second gated oscillator circuits, thereby extracting a reproduced clock. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
