发明名称 TEST FACILITATION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To facilitate a test at a real operation frequency of an integrated circuit having two or more functional blocks which operate in asynchronization with one another. SOLUTION: The integrated circuit 40 having two or functional blocks (42, 43, 44) which operate in asynchronization with one another, is provided with a mode setting pin 41 for inputting a test mode signal, clock frequency dividing circuits 54-56 each of which divides the frequency of either one clock signal out of clock signals to be used in a usual operation mode and inputted from clock inputting pins 45-47, and clock selection means 57-59 each of which performs a switchover between either one out of two or more clock frequency divided signals as the outputs of the dividing circuits 54-56 and a clock signal to be used in the usual operation mode, and outputs the signal to either one of the functional blocks 42-44. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005043226(A) 申请公布日期 2005.02.17
申请号 JP20030277853 申请日期 2003.07.22
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 ICHIGUCHI SEIDO;TANAKA TAKATOSHI
分类号 G01R31/28;H01L21/822;H01L27/04;(IPC1-7):G01R31/28 主分类号 G01R31/28
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