| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce power consumption and also to prevent outputs SL1-SLn of a shift register from overlapping one another in a shift register 11, in which level shifters LS1-LSn for shifting the level of clock signals CK, CKB having a smaller amplitude than that of a drive voltage for applying to respective flip flops F1-Fn are provided for each block. <P>SOLUTION: Control circuits CNi (i=1-n) are provided for each block and the level shifter LSi+1 at the next stage is controlled by using an output of any one of the shift registers 11 to the outside and an output of the flip flop Fi. Accordingly, the level shifter of the block concerned can be operated only for the minimum period when the block concerned outputs a shift output, and hence the power consumption can be reduced and the outputs SL1-SLn can be prevented from overlapping mutually. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
