TRENCH GATE TYPE SEMICONDUCTOR DEVICE AND ITS MANUFACTURING DEVICE

摘要

PROBLEM TO BE SOLVED: To provide a trench gate type MOS FET of low ON resistance. SOLUTION: An n--type drift region 2 and a p-channel region 3 are laminated one by one on an n+-type substrate 1. An n+-type source region 4 and a p+-type body region 5 are formed to a stripe in an upper surface of the p-channel region 3. A trench 7 passes through the p(n)-type channel region 3 and attains to the n--type drift region 2, and a gate 9 constituted of polycrystalline silicon is buried via a gate insulating film 8. The n+-type source region 4 and the p+-type body region 5 extend from the p(n)-type channel region 3 to a source electrode 20 and cross the trench 7. The upper surface of the gate 9 is located above the upper surface of the p-channel region 3. A layer insulating film 10 is inside the trench 7, and its upper surface is located below an opening of the trench 7. The source electrode 20, the n+-type source region 4 and the p+-type body region 5 are electrically connected each in a side wall of the trench 7. COPYRIGHT: (C)2005,JPO&NCIPI