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发明名称
通路可规划闸阵列互连体架构
摘要
描述一种提供闸阵列积体电路之互连之接线部份之分段架构。藉由接线部份间和至半导体基板表面之可选择之通路来提供规划。二互连层之接线部份配置于二方向上,且一可规划缓冲器可视通路接触如何藉由承载缓冲器讯号之接线部份来形成至缓冲器来在一可选择之方向上驱动讯号。
申请公布号
TW200507223
申请公布日期
2005.02.16
申请号
TW092135639
申请日期
2003.12.16
申请人
豹逻辑公司
发明人
史帕德纳 戴特;王戴尔
分类号
H01L23/52
主分类号
H01L23/52
代理机构
代理人
恽轶群;陈文郎
主权项
地址
美国
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