High speed pipeline architecture with high update rate of associated memories

摘要

A high speed pipeline architecture comprising a plurality of successive processing stages or pipestages (Stage 1 - n) coupled in cascade to forward user packets of data. Each pipestage is adapted to be coupled to at least one memory unit (Data 1 - n) storing a forwarding table. The memory unit is preferably of the RDRAM memory technology, and the forwarding table preferably an IP packet forwarding table. <??>A data manager (DM) is used to update the memory units by transferring maintenance data through the pipestages. Since the maintenance actions on the memory units are passed through the same pipeline that forwards the user packets, these operations are mutually ordered and high update rates on the memory units can be achieved without losing any incoming user packets. <IMAGE>