Phase comparator and clock recovery circuit

摘要

A phase comparator in a PLL comprises a phase comparing portion (17) having inputs for data (6) and clock (5) signals and generates leading (U4) and lagging (D4a) pulses to be supplied to a charge pump. A correcting pulse generation portion (18) generates a correction pulse from the input clock and data signals. A resetting portion (19) is supplied with the correction pulse, the clock signal and the leading and lagging pulses and generates a reset pulse to reset the phase comparator portion. The correction pulse is also supplied to a pulse correcting portion (20) to remove false pulses contained in the incomplete lagging pulse train. <IMAGE>