| 摘要 |
The non volatile memory device integrates, in one and the same chip (100), the array (2) of memory cells, a voltage regulator (REG) which supplies a regulated operating voltage (Vr) to a selected word line (LWL1), and a short circuit detecting circuit (10). The short circuit detecting circuit detects the output voltage (IM1) of the voltage regulator (REG), which is correlated to the current (Iw) for biasing the cells (3) of the word line selected (LWL1). Once settled to the steady state condition, the output current (IM1) assumes one first value (IM1') in the absence of short circuits, and one second value (IM1") in the presence of a short circuit between the word line selected (LWL1) and one or more adjacent word lines (LWL0, LWL2, ..., LWLn). The short circuit detecting circuit (10) compares the output current (IM1) of the voltage regulator (REG) with a reference value (Iref) and generates at output a short circuit digital signal (Vo) which indicates the presence or otherwise of a short circuit. <IMAGE> |
