发明名称 Hierarchy of fault isolation timers
摘要 In the present invention, a coordinated hierarchy of timing mechanisms preferably cooperate to report errors at different operational levels of a complex of computing devices. Preferably, each timer is able to identify a failure condition at its own level of operation and transmit a time-out condition to a higher level device which may also be a timer. Upon generation of a time-out condition, a system component experiencing a fault condition preferably continues to operate in a degraded mode, informs devices attempting to communicate with the faulty component of a status of the fault condition, and preferably proceeds to identify and correct a failure which caused the time out condition. The timers may be implemented in hardware or software.
申请公布号 US6857086(B2) 申请公布日期 2005.02.15
申请号 US20030419558 申请日期 2003.04.21
申请人 HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. 发明人 SHAW MARK
分类号 G06F11/30;G06F1/14;G06F11/00;H02H3/05;H04L1/22;(IPC1-7):G06F11/00 主分类号 G06F11/30
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