Pipeline array

摘要

A pipeline array includes a register, a pipeline clock input, and Narrow Pulse Triggered Latches (NPTL) stages connected in series. Each NPTL stage includes a Latch Pulse Generator (LPG) and a parallel set of single latches clocked by the LPG. The latches provide the parallel data input and the parallel data output of the stage. Each LPG provides a narrow latch clock pulse in response to a Pipeline Clock Pulse (PCP) supplied to the register and the last stage of latches. Each PCP arrives at each preceding LPG in the array after a delay provided by intervening time delay units. The delays increase for each preceding stage with the least delay at the penultimate stage and with the greatest delay at the first stage. The data input of the first stage is connected to the output of the register. The data input of the each of other stage is connected to the data output of the preceding stage in the array.