发明名称 Clock divider circuit
摘要 A system that includes a first circuit configured generate a first set of encoded signals in response to a first clock signal and a second circuit configured to generate a second set of encoded signals in response to the first clock signal is provided. The system also includes a third circuit configured to generate a first pulse signal and a second pulse signal in response to the first set of encoded signals and the second set of encoded signals, and a fourth circuit configured to generate a second clock signal in response to the first pulse signal and the second pulse signal.
申请公布号 US6856184(B2) 申请公布日期 2005.02.15
申请号 US20030346689 申请日期 2003.01.15
申请人 AGILENT TECHNOLOGIES, INC 发明人 HIDAI TAKASHI
分类号 G06F1/06;G06F1/08;H03K5/00;(IPC1-7):H03K21/00 主分类号 G06F1/06
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